Method of ion implantation for achieving desired dopant concentration

ABSTRACT

A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

FIELD OF THE INVENTION

[0001] The present invention is directed to semiconductor devicesincorporating junctions of varying conductivity types designed toconduct current and methods of making such devices. More specifically,the present invention is directed to metal-oxide field-effecttransistors (MOSFETs) having uniquely-determinable threshold voltagesand methods for fabricating integrated circuits incorporating suchdevices.

BACKGROUND OF THE INVENTION

[0002] As is known to those skilled in the art, mostmetal-oxide-semiconductor field effect transistors (MOSFETs) are formedin a lateral orientation, with the current flowing parallel to the planeof the substrate or body surface in a channel between a source regionand a drain region.

[0003] For an enhancement-mode n-channel MOSFET, the substrate is dopedp-type and the source and drain regions are diffused or implanted withan n+ doping. A thin oxide layer separates the conductive gate from thesilicon surface region between the source and drain regions. No currentflows from the drain to the source region unless a conducting n-typechannel is formed between the two n-type regions. When a positivevoltage is applied to the gate relative to the substrate which istypically connected to the source, positive charges are in effectdeposited on the gate metal and in response, negative charges areinduced in the underlying silicon. These negative charges, that ismobile electrons, are formed within a thin inverted surface region ofthe silicon surface. These induced mobile electrons form the channel ofthe MOSFET and allow current to flow from the drain to the source. Theeffect of the gate voltage is to vary the conductance of the inducedchannel. Lowering the conductance lowers the barrier for the electronsto surmount between the source, channel and the drain. If the barrier issufficiently reduced, by the application of a gate voltage in excess ofa threshold voltage (V_(T)) then there is a significant electron flowfrom the source to the drain. The threshold voltage is the minimum gatevoltage required to induce the channel, i.e., form the inverted regionto drive the MOSFET into a conducting state. For an n-channel device,the positive gate voltage must be larger than a positive thresholdvoltage before a conducting channel is induced. Similarly, in a p-typechannel device (which is made on an n-type substrate with a p-typesource and drain implants or diffusions) requires a gate voltage morenegative than some threshold value to induce the required positivecharge (comprising mobile holes) in the channel.

[0004] The threshold voltage is a function of several MOSFET physicaland electrical parameters, including the oxide capacitance, the oxidethickness, the difference in work functions between the gate material(typically metal or polysilicon) and the silicon substrate, the channeldoping and the impurity ion charge storage within the gate oxide. Aswill be discussed below, and according to the prior art, typically thesubstrate doping concentration is varied to form MOSFETs with differingthreshold voltages on a single integrated circuit.

[0005] A plurality of planar n-channel MOSFET active devices fabricatedon an integrated circuit chip are shown in the FIG. 1 cross-sectionalview. A substrate 9 comprises a p+ region 50 and a p− layer 52, thelatter typically grown by an epitaxial technique from the p+ region.MOSFETs 2, 4 and 6 are fabricated in the substrate 9. The MOSFET 2 isseparated from the MOSFET 4 by a LOCOS (local oxidation on siliconsubstrate) region 10. Similarly, the MOSFET 6 is separated from theMOSFET 4 by a LOCOS region 12. Alternatively, the MOSFETS 2, 4 and 6 maybe electrically isolated by shallow trench isolation (STI) techniques,wherein an anisotropic etch forms a trench in the region between twoactive devices. The is filled with an insulative material.

[0006] The MOSFET 2 comprises a gate 14, a source region 16 and a drainregion 18 diffused in an n-type well 20. The MOSFET 4 comprises a gate28, a source region 30 and a drain region 32 diffused in a p-type well34. Finally, the MOSFET 6 comprises a gate 38, a source region 40 and adrain region 42 diffused in an n-type well 44. The gates 14, 28 and 38are separated from the substrate 9 by a silicon dioxide layer 46, alsoreferred to as a gate oxide layer.

[0007] As FIG. 1 is intended to be a simplified representation of aportion of an integrated circuit, the various contacts, interconnects,vias and metal layers are not shown and the features are not drawn toscale. It is particularly advantageous, especially in digitalapplications, to fabricate a combination of n-channel and a p-channelMOSFETs on adjacent regions of a chip. This complementary MOSFET (CMOS)configuration is illustrated in the form of a basic inverter circuit inFIG. 2, comprising a PMOSFET 60 and an NMOSFET 62. The drains of theMOSFETs 60 and 62 are connected together to form the output terminal(V_(out)). The input terminal (V_(in)) is formed by the commonconnection of the MOSFET gates. The operating voltage is designated byV_(D). In the FIG. 2 schematic, the PMOSFET 60 can be implemented by thestructure of the MOSFET 2 in FIG. 1. The NMOSFET 62 can be implementedby the structure of the MOSFET 4 of FIG. 1.

[0008] State-of-the-art integrated circuit fabrication combines manydifferent functions and subsystems onto a single chip, for example,combining different types of logic circuits, logic families and memoryelements. For optimal performance and minimal power consumptionindividual devices on the integrated circuit may be operated atdifferent operating voltages, i.e., the V_(D) and V_(S) values. Thus,the active devices must be fabricated with the necessary physicalcharacteristics to accommodate the selected operating voltage. But increating physical devices with these characteristics, it is alsodesirable to minimize and simplify the number of fabrication processsteps.

[0009] For example, each of the MOSFETs 2, 4 and 6 of FIG. 1, may bedesigned to operate at a different operating voltage, i.e., V_(D)/V_(S)and/or at a different threshold voltage, V_(T). Generally, it isdesirable to establish the device operating voltage at the minimum valuethat provides the required performance to minimize the power consumptionof the devices, and thus overall, the power consumption of the chip. Itis known, however, that there is a counter-effect; as the deviceoperating voltage is reduced the operating speed of the device is alsoreduced. Therefore, to establish the optimum value for both of theseparameters, it is necessary to operate the individual devices atoperating voltages consistent with the required speed performance.

[0010] Given that there may be multiple operating voltages on a chip,there may also be multiple output voltages produced by the activeelements and circuits of the chip. Thus the input circuit or deviceresponsive to the preceding output voltage must be able to accommodatethat output voltage and the active device must be designed to turn-on atthe appropriate input voltage. For MOSFET and junction field-effectdevices (JFETs) this turn-on voltage is the threshold voltage, the valueof which is established by certain physical parameters of the device, asdiscussed above.

[0011] The prior art process of forming a plurality of MOSFETs withdifferent threshold voltages is illustrated in FIGS. 3 through 6. At theconclusion of this process, each tub or well has a different dopingdensity and therefore the MOSFET formed in each tub has a differentthreshold voltage. As shown in FIG. 3, a p+ substrate 100 carries anepitaxially grown p− layer 102 in which a plurality (three in thisexample) of n-type tubs are formed. Those skilled in the art recognizethat the concepts presented are also applicable to the formation ofp-type tubs or wells in a p or n-type substrate. To form the tubs,certain regions of the epitaxial layer 102 are masked by masks 104, 106,108 and 110, with the space between these masks defining the tubregions. The arrows indicate the implantation of phosphorous or arsenicto create the n-type wells. Typically, the implant energy is 10 to 100keV with a dose of 1E12 to 5E14 per cm².

[0012] As shown in FIG. 4, this implantation step forms three n-typewells, 120, 122 and 124, each having the same doping density. If allother physical and electrical parameters for the three wells areequivalent, then the threshold voltages at this point in the process arealso equivalent. FIG. 4 further illustrates the application of a secondimplantation to the well 120, while the wells 122 and 124 (and otherareas of the substrate 100) are masked by masks 126 and 128. Thus thefinal doping density and the threshold voltage for the MOSFET formed inthe well 120 are determined by the parameters of the FIG. 4 implant intothe well 120.

[0013] Continuing with FIG. 5, the wells 120 and 124 are masked by masks130 and 132, respectively. An additional implant step is executed forthe well 122 to establish the final doping density and threshold voltagefor the MOSFET formed therein. Finally, as shown in FIG. 6, the wells120 and 122 are masked with a mask 134 and the remainder of thesubstrate 100 is masked, as necessary, by a mask 136. Now an additionalimplant is made in the well 124 for establishing its doping density andthus the threshold voltage for the MOSFET formed therein. Although thisprocess is readily extendable to any number of MOSFETs on an integratedcircuit, note that it requires a number of unique masks and maskingsteps based on the number of threshold voltages required on theintegrated circuit. It is always desirable in the fabrication ofintegrated circuits to reduce the number of masks, as they are expensiveto design and manufacture, and the number of fabrication process steps.

[0014] As is well known to those skilled in the art, at this pointfabrication of the MOSFETs proceeds conventionally. For each MOSFET, agate oxide is grown or deposited followed by formation of the gate. Thegate serves as a mask for a first low-dose implant to form the lightlydoped drain and source regions. A relatively thick layer of silicondioxide is then deposited, for instance, by chemical vapor depositionand certain portions thereof are anisotropically etched, leaving onlytwo sidewall spacers adjacent the gate. The spacers serve as a mask fora high-dose dopant implant to form the source and drain regions. After adrive-in diffusion step, the source and drain regions and the adjacentlightly-doped regions are formed.

BRIEF SUMMARY OF THE INVENTION

[0015] To provide further advances in the formation of multiplethreshold voltages for semiconductor devices, a method is provided forforming MOSFET devices having different threshold voltage values.

[0016] According to one embodiment of the invention, an integratedcircuit semiconductor device includes a plurality of doped tubs or wellsin which the source, drain and channel regions are later formed. Thedopant density in each well is established to produce the requiredthreshold voltage for the MOSFET device formed in that well. To createdifferent doping levels in the tubs, a tilted implant is performedthrough patterned lines of photoresist, polysilicon, silicon dioxide,silicon nitride, or any material that blocks or impedes the transmissionof implanting ions therethrough. Each line in the patterned layer has adifferent width for controlling the number of implanting ions thatpenetrate the patterned layer and enter the substrate in the regionadjacent the line. For the same ion implantation energy (typicallymeasured in keV) more ions will penetrate a thinner line in the layerthan a thicker line. Thus a tub formed by implantation through anadjacent thinner pattern line has a higher doping density and the MOSFETformed therein has a higher threshold voltage.

[0017] The method according to the present invention reduces the costand complexity of forming MOSFETs with different threshold voltages. Aplurality of MOSFETs with a range of threshold voltage values can beformed simultaneously with no additional masking steps.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention can be more easily understood and thefurther advantages and uses thereof more readily apparent, whenconsidered in view of the description of the preferred embodiments andthe following figures in which:

[0019]FIG. 1 is a cross-sectional view of a prior art MOSFET devices;

[0020]FIG. 2 is a partial schematic of a prior art CMOS integratedcircuit;

[0021]FIGS. 3 through 6 illustrate, in cross-section, a prior artprocess for forming MOSFETs with different threshold voltages duringsequential process steps;

[0022]FIGS. 7 and 8 illustrate prior art integrated circuits inschematic form;

[0023]FIGS. 9 through 17 illustrate, in cross-section, a process forforming MOSFETs with different threshold voltages according to theteachings of the present invention.

[0024] In accordance with common practice, the various describedfeatures are not drawn to scale, but are drawn to emphasize specificfeatures relevant to the invention. Reference characters denote likeelements throughout the figures and text.

DETAILED DESCRIPTION OF THE INVENTION

[0025]FIG. 7 is a partial schematic of a prior art CMOS integratedcircuit 168 illustrating two pairs of CMOS devices. PMOSFET 170 andNMOSFET 172 form a first CMOS pair; PMOSFET 174 and NMOSFET 176 form asecond CMOS pair. V_(in) ₁ is the gate driving signal for the PMOSFET170 and the NMOSFET 172, which creates an output signal (V_(out) ₁ ) atthe common drain connection. V_(in) ₂ is the gate signal for the CMOSpair PMOSFET 174 and NMOSFET 176, which produces an output signalV_(out) ₂ . Note further that PMOSFET 170 is responsive to a drainvoltage V_(dd.), and PMOSFET 174 is responsive to a drain voltageV_(dd2). The drain voltages V_(dd1) and V_(dd2) may be produced off-chipor on-chip, although they are illustrated in FIG. 7 as originating froman off-chip voltage source. Because in one embodiment V_(dd1) andV_(dd2) are not equal, V_(out) ₁ is not equal to V_(out) ₂ . In atypical circuit configuration, both output signals V_(out) ₁ and V_(out)₂ drive the next active element in a cascaded circuit chain. Forinstance, V_(out) ₁ can serve as the input signal V_(in) ₂ , and V_(out)₂ can be supplied to another element in the integrated circuit 168 orsent off-chip. V_(in) ₁ may be produced by another circuit within theintegrated circuit 168 or originate from an off-chip source. In anycase, it is clear that the use of different operating voltages (V_(dd1)and V_(dd2)) and input/output voltages (V_(in) ₁ , V_(in2), V_(out) ₁and V_(out) ₂ ) may require the formation of MOSFETs with differentthreshold voltages. As a result, for example, the CMOS pair comprisingPMOSFET 170 and NMOSFET 172 may be fabricated with a first thresholdvoltage and the CMOS pair PMOSFET 174 and NMOSFET 176 may be fabricatedwith a second threshold voltage.

[0026]FIG. 8 illustrates another exemplary integrated circuit 178comprising an NMOSFET device 182 and an NMOSFET device 184. As in FIG.7, the input signals V_(g) ₁ and V_(g) ₂ may not be in the same voltagerange and thus the NMOSFET devices 182 and 184 must each be fabricatedto accommodate a different threshold voltage input signal. Note, in thiscase that the drain terminals of both NMOSFET 182 and NMOSFET 184 areconnected to a single supply voltage, V_(dd1). The fact that eachtransistor is operated from the same supply voltage is not necessarilydeterminative of the threshold voltage required to accommodate the gateinput signals. Because the MOSFET threshold voltages are chosen based ona number of design and operating characteristics of the integratedcircuit, it is possible that several different threshold voltage MOSFETswill be required on a state-of-the-art integrated circuit.

[0027] With reference to FIG. 7, it can be seen that the PMOSFET 170 andNMOSFET 172 can be fabricated with a first threshold voltage, while thePMOSFET 174 and the NMOSFET 176 can be fabricated with a secondthreshold voltage. As will be appreciated by application of theinvention to the circuit of FIG. 8, the relevance of the presentinvention is not limited to CMOS applications, but can instead beapplied to individual MOSFETs, whether such MOSFETs are interconnectedto form logic circuits, signal processing circuits, basic CMOS buildingblock circuits or memory devices.

[0028] As shown in FIG. 9, the first step in forming a plurality ofMOSFETs and independently determining the threshold voltage for each,begins by implanting the wells or tubs. In FIG. 9, a substrate 200(doped p+) underlies an epitaxially grown p− layer 202. Mask elements204, 206, 208 and 210 are placed over the epitaxial layer 202 andphosphorous or arsenic dopant ions are implanted into the epitaxiallayer 202 in the open spaces between the mask elements 204, 206, 208 and210. The result is illustrated in FIG. 10, showing three n-type wells220, 222 and 224. Those skilled in the art recognize that a greater orfewer number of wells can be formed according to the teachings of thepresent invention. Further, in another embodiment p-type wells forcreating a p-channel MOSFET device can be formed by the same technique,using boron ions for the implant step. In one embodiment, each well 220,222 and 224 is isolated from the adjacent well by a local oxidation ofsilicon (LOCOS) region 225 and 226. In another embodiment, shallowtrench isolation can be utilized.

[0029] A layer of photoresist, silicon nitride, silicon dioxide or othermaterial that is partially transmissive to the ions to be implantedthrough the mask element is formed over the epitaxial layer 202. A maskelement having a plurality of different-width lines is created, and themask is used to pattern the layer such that a line is located proximateeach of the n-type wells that are to be implanted, for example, then-type wells 220, 222 and 224. In the FIG. 11 exemplary embodiment,three such patterned lines 230, 232 and 234 are shown. The lines are ofa different width, which in turn controls the doping density in theadjacent well due to the use of a tilted ion implant through the lines.Tilt angles of between about 7° and 60° are typical, although tiltangles between 1° and 89° are possible.

[0030] The arrowheads 236, 238 and 240 represent the tilted implantationof dopant ions in the wells 220, 222 and 224 respectively. Some of theions are absorbed by the lines 230, 232 and 234, where the absorptionrate is a function of the individual line width and the line material(each candidate material has a unique transmission coefficient for aspecific ion). Thus the well 222 receives a lower implant doping thanthe well 224, because the line 232 is wider than the line 234. As aresult, the threshold voltage for the MOSFET to be formed in the well222 is lower than the threshold voltage of the MOSFET to be formed inthe well 224. The line widths and material are selected to achieve therequired MOSFET threshold voltage by controlling the implanted dopantdensity. Since the MOSFET channel region is formed in the well, MOSFETswith different threshold voltages can be fabricated throughout theintegrated circuit using a single mask to form lines of varying width.

[0031] It is noted that the region of the well nearest the line mayreceive a higher implant dose than a region farther from the line as theimplanting ions travel a greater distance in the masking layer in thelatter case. See the example of FIG. 12A, illustrating a mask line 260positioned above a semiconductor substrate 262, and a plurality ofimplanting rays 264. Note that the mask line is sufficiently high topermit all the implanting rays 264 to pass therethrough. FIG. 12Billustrates the doping profiles in the semiconductor substrate 262; theimplant profile is represented by a solid line and the post-diffusionprofile as a dashed line. To the extent this creates a lateral variationin the doping profile, the device threshold voltage is determined by thecomposite or average (loping density in the semiconductor substrate 262.

[0032] In the embodiment of FIG. 13A, a mask line 270 is positionedabove a semiconductor substrate 272, but in this case the mask line 270is not high enough for all the implant rays 274 to pass therethrough.Thus a number of the implant rays 274 pass through the mask line 270 andothers pass above the mask 270. The resulting dopant profiles areillustrated in FIG. 13B, where the implanted profile is represented by asolid line and the post-diffusion profile by a dashed line. In thisembodiment, the device threshold voltage is determined by the average orcomposite doping density in the semiconductor substrate 272.

[0033] In another embodiment of the present invention, a second implantis performed to create a relatively uniform dopant distribution acrossthe well. As shown in FIG. 14, a mirror image of the FIG. 11 linepattern, comprising lines 290, 292 and 294 is formed on the oppositeside of each well 220, 222 and 224, and a second tilted implant isperformed from the opposite side as shown. Having been implanted fromboth sides of the well, tile dopant density across the well isrelatively uniform.

[0034] Because a single mask is typically used to pattern the line widththroughout the integrated circuit (or two masks if a more uniform dopantdensity is desired), the process according to the present invention isconsiderably less expensive than the prior art process which requiresmultiple masks to form MOSFETs with different threshold voltages. In oneembodiment of the present invention, the lines 230, 232, and 234 areformed of photoresist material. In other embodiments, the lines areformed from polysilicon, silicon nitrite or silicon dioxide, all ofwhich are common expedients used in conventional integrated circuitfabrication. To determine the width of each line, consideration must begiven to the line material employed, as each material has a differenttransmission characteristic for the ions to be implanted.

[0035] From this point, the fabrication process proceeds according toconventional MOSFET fabrication steps. For each MOSFET, a gate oxide isgrown or deposited and the gate is then formed. The gate serves as amask for a first low-dose implant to form the lightly doped drain andsource regions, also referred to as drain and source extensions. Arelatively thick layer of silicon dioxide is then deposited, forinstance, by chemical vapor deposition, and anisotropically etched,leaving only two sidewall spacers adjacent the gate. The spacers serveas a mask for a high-dose dopant implant to form the source and drainregions. After drive-in diffusion, the source and drain regions and theadjacent lightly-doped regions are formed.

[0036] As the MOSFET dimensions continue to shrink, certaindisadvantageous operational characteristics develop, including draininduced barrier lowering. This phenomena, which occurs when there isunintended electrostatic interaction between the source and drainregions, is typically caused by improperly scaling of the deviceregions, i.e., the source and drain regions are too thick or the channeldoping is too low. The result of drain induced barrier loading ispunchthrough leakage or breakdown between the source and the drain, andthe loss of gate control over the channel current. To avoid draininduced barrier lowering, the source and drain junctions must be madesufficiently shallow as the channel lengths are reduced. Also, thechannel doping must be sufficiently high to prevent the drain fromexercising control over the source junction, but increasing the dopingconcentration throughout the channel region may undesirably increase thethreshold voltage. Thus the channel doping is increased by performinglocalized dopant implants in the channel near the source and drainregions. The localized implants are known as halo or pocket implants.The higher doping near the source and drain regions reduces the sourceand drain depletion width and prevents interaction between these tworegions. The halo process uses a tilted implant geometry and istypically performed after gate formation. The implant results in anon-uniform lateral profile under the gate, while the lateral profile inthe source and drain regions remains relatively uniform.

[0037]FIG. 15 illustrates such a halo implant in a semiconductorsubstrate 300. Implanting adjacent a gate mask 302 (i.e., the gateselves as the mask) over a region 304 of the semiconductor substrate 300limits the doping concentration within the region 304. A line 310 inFIG. 15B represents an exemplary dopant concentration profile within thesemiconductor substrate 300. After the halo implant, the dopantconcentration is illustrated by a line 310. As shown, the doping profileoutside the region 304 is relatively uniform, then becomes non-uniformunder the gate mask 302. As applied to a MOSFET device, the region 304represents the channel and the region of uniform doping concentrationrepresents either the source or drain regions.

[0038] The teachings of the present invention can be used in conjunctionwith the halo implant as follows. As shown in FIG. 16A, two mask lines350 and 352 overlie a substrate 354, including a tub or well region 355of a MOSFET. Dashed lines illustrate the approximate location of thesource/drain regions 356 and 358, which will be formed at a later stagein the process in the tub region 355. Ion implant rays 360 and 362 passthrough the masked lines 350 and 352, respectively, to dope the tub 355creating the doping profile illustrated in FIG. 16B, representing thedoping profile along a horizontal plane through the source/drain regions356 and 358.

[0039] Next, a halo implant is performed using a gate mask 370 andimplanting ion rays 372 and 374 as illustrated in FIG. 17A. Withreference to FIG. 17B, the initial doping concentration is illustratedby a line 376 resulting from the process illustrated in FIG. 16A. Thehalo concentration is illustrated by a line 378 and the totalconcentration by a line 380. The net dopant concentration in thesource/drain regions 356 and 358 is about two orders of magnitudegreater than the concentration in the tub regions 355 below thesource/drain regions 356/358. The latter concentration is illustrated inFIG. 17C. Note that it has the same shape as the concentrationillustrated in FIG. 17B by the line 374. The dopant profiles in FIG. 17Balso represent the z-direction (i.e., into the plane of the page) dopantconcentrations.

[0040] The dopant profile of FIG. 17B is advantageous to reduce narrowwidth effects in MOSFETs having a gate width of less than about 1 μm.Specifically, one negative narrow width effect is an increase in thethreshold voltage as, the channel width decreases. The dopant profile ofFIG. 17B, with the higher concentrations in the regions away from thegate, reduces this threshold voltage increase.

[0041] Simulation results according to the present invention have shownthat with a polysilicon line width of 0.65 micrometers, an implantedsurface doping concentration of 1E17/cm3 is produced, and assumingcertain physical characteristics for the simulated MOSFET, the resultingthreshold voltage is 0.025 volts. When the line width is changed to 0.20micrometers, the surface (loping concentration is 7E17/cm3 and thesimulated threshold voltage is 0.400 volts.

[0042] A process has been described as useful for forming MOSFET tubswherein the tubs comprise the channel region and have a controlleddopant density. While specific applications of the invention have beenillustrated, the principals disclosed herein provide a basis forpracticing the invention in a variety of ways and in a variety circuitstructures, including structures formed with Group III-V compounds andother semiconductor materials. Although the exemplary embodimentspertain to tub-based MOSFETs, the teachings of the present invention canbe applied to any devices or device region where the devicecharacteristics are dependent on the doping concentration. For example,the dopant concentrations of silicon-on-insulator and bipolar junctiontransistors regions can be controlled by the tilted implant through amaterial layer as discussed above. For example, bipolar junctiontransistors with different gain values can be formed in an integratedcircuit by controlling the base doping concentration using thetechniques of the present invention. Also. numerous variations arepossible within the scope of the invention, which is limited only by theclaims that follow.

What is claimed is:
 1. A method for fabricating a semiconductor deviceregion comprising: forming a doped semiconductor region on asemiconductor layer; forming a first material line proximate the dopedsemiconductor region on the top surface of the semiconductor layer;performing a first tilted ion implantation through the first materialline, wherein the ion beam intersects the first material line at anangle with respect to the top surface of the semiconductor layer suchthat the ion beam passes through the first material line prior tostriking the doped semiconductor region, and wherein the implanted iondosage reaching the doped semiconductor region to increase the dopantconcentration thereof is dependent on the material line width.
 2. Themethod of claim 1 wherein the step of forming the material linecomprises forming a first layer over the semiconductor layer, patterningthe first layer to identify the location of the material line, andremoving the material of the first layer except for the material line.3. The method of claim 1 wherein the material of the first material lineis selected from among silicon nitride, silicon dioxide, photo resistand polycrystalline silicon.
 4. The method of claim 1 wherein the tiltangle is in the range of about 1 to 89 degrees.
 5. The method of claim 1wherein the width of the material line is selected to control the ionimplantation dosage reaching the doped semiconductor region.
 6. Themethod of claim 1 wherein the height of the material line is selected tocontrol the ion implantation dosage reaching the doped semiconductorregion.
 7. The method of claim 1 further comprising: forming a secondmaterial line proximate the doped semiconductor region on the opposingside of the doped semiconductor region from the first material line;performing a second tilted ion implantation through the second materialline, wherein the ion beam intersects the second material line at anangle with respect to the top surface of the semiconductor layer suchthat the ion beam passes through the second material line prior tostriking the doped semiconductor region.
 8. The method of claim 7wherein after the first and the second tilted ion implantations thelateral dopant concentration in the doped semiconductor region issubstantially uniform.
 9. The method of claim 1 wherein the dopantconcentration is laterally non-uniform.
 10. A method of doping asemiconductor device region comprising: forming a plurality of dopedsemiconductor regions on a semiconductor layer by one or more dopantintroduction steps, wherein at least one doped semiconductor region isassociated with one of a plurality of semiconductor devices; forming amaterial line proximate at least one of the plurality of semiconductorregions; performing an ion implantation wherein the ion beam intersectsthe material line at an angle with respect to the top surface of thesemiconductor layer such that the ion beam passes through the materialline prior to striking the proximate semiconductor region, and whereinthe implanted ions further increase the doping concentration of thedoped semiconductor region, as determined by the width of the materialline.
 11. The method of claim 10 wherein the doped semiconductor regionis a semiconductor well.
 12. The method of claim 10 wherein the materialof the material line is selected from among silicon nitride, silicondioxide, photo resist and polycrystalline silicon.
 13. The method ofclaim O further comprising: forming an opposing material line proximateand on the opposing side of the doped semiconductor region from thematerial line; and performing a second tilted ion implantation throughthe opposing material line, wherein the ion beam intersects the opposingmaterial line at an angle with respect to the top surface of thesemiconductor layer such that the ion beam passes through the opposingmaterial line prior to striking the doped semiconductor region.
 14. Themethod of claim 10 wherein a plurality of material lines are formed,wherein the width and the height of each material line is selected toachieve the desired doping concentration in the doped semiconductorregion.
 15. A method for fabricating a plurality of field effecttransistors, comprising: forming a plurality of doped semiconductorwells on a semiconductor substrate, wherein each doped semiconductorwell is associated with a field-effect transistor; forming a pluralityof material lines each proximate a doped semiconductor well, whereineach one of the plurality of material lines has a predetermined width;performing a tilted ion implantation through each one of the materiallines such that the ion beam intersects each one of the plurality of thematerial lines at an acute angle with respect to the top surface of thesemiconductor layer and strikes the proximate doped semiconductor well,and wherein the implanted ions further increase the doping concentrationof the doped semiconductor well; in each of the plurality ofsemiconductor wells, forming an oxide layer on a region of thesemiconductor layer, wherein the region below the oxide layer defines achannel region; forming a gate region over the oxide layer in each oneof the plurality of semiconductor wells; and forming a source region anda drain region in each one of the plurality of doped semiconductor wellswith the channel region therebetween; wherein the combination of asource region, a drain region and a gate associated with each one of theplurality of doped semiconductor wells forms a field-effect transistor,and wherein the dopant density of the channel region is dependent on thetransmission of ions through the material line, and wherein thethreshold voltage of each field-effect transistor of the plurality offield-effect transistors is dependent on the dopant density.
 16. Themethod of claim 15 wherein after the step of forming the dopedsemiconductor wells, the doped semiconductor wells have a minimal dopantdensity.
 17. The method of claim 15 wherein the transmissive propertiesof each material line are a function of the material line width.
 18. Themethod of claim 15 wherein the material line comprises silicon nitride,silicon dioxide, photo resist or polycrystalline silicon.
 19. The methodof claim IS further comprising: forming an opposing material lineproximate and on the opposing side of the doped semiconductor well fromthe material line; and performing a second tilted ion implantationthrough the opposing material line, wherein the ion beam intersects theopposing material line at an angle with respect to the top surface ofthe semiconductor layer such that the ion beam passes through theopposing material line prior to striking the doped semiconductor well.20. The method of claim 15 wherein the width and the height of each oneof the plurality of material lines is selected to achieve the desiredthreshold voltage for the associated field-effect transistor.
 21. Asemiconductor device comprising a plurality of field effect transistors,wherein a first of the transistors is formed in a tub region of a firstconductivity type, characterized by a threshold voltage different fromthat of a second of the transistors, the first transistor including agate structure and first and second source/drain regions of a netconductivity of a second conductivity type formed in the tub region,each source/drain region formed along a lateral surface region of thedevice on an opposing side of the gate region, each source/drain regionincluding a first portion extending toward the gate region and a secondportion extending away from the gate region, one of the source drainregions characterized by a tub dopant concentration of the firstconductivity type along the lateral surface region with a relativelyhigh first tub dopant concentration in the second portion and arelatively low tub dopant concentration extending from between thesecond portion and the first portion toward the gate structure.
 22. Thedevice of claim 21 wherein the relatively low tub dopant concentrationin said one source/drain region extends to the gate structure.
 23. Thedevice of claim 21 wherein the relatively high tub dopant concentrationin said one source/drain region is less than 1E19 per cm³ and therelatively low dopant concentration in said one source/drain region isless than 9E18 per cm³.
 24. The device of claim 21 wherein therelatively high tub dopant concentration in said, one source/drainregion is between 1E16 per cm³ and 1E19 per cm³ and the relatively lowdopant concentration in said one source/drain region is less than 9E18per cm³.
 25. The device of claim 21 wherein the relatively high tubdopant concentration in said one source/drain region is approximately2E18 per cm³ and the relatively low dopant concentration in said onesource/drain region is approximately 1E18 per cm³.
 26. A semiconductordevice comprising a plurality of field effect transistors wherein afirst of the transistors is formed in a tub region of first conductivitytype, the first transistor including a gate structure and first andsecond source/drain regions of a net conductivity of a secondconductivity type formed in the tub region, the tub region below onesource/drain region including a first portion extending along the onesource/drain region toward the gate region and a second portionextending along the one source/drain region away from the gate region,the first portion characterized by a low tub dopant concentration of thefirst conductivity type relative to the second portion tub dopantconcentration.
 27. The device of claim 26 wherein the low first portiontub dopant concentration extends to below die gate structure.
 28. Thedevice of claim 26 wherein the tub dopant concentration in the secondportion is less than 1E19 per cm³ and the tub dopant concentration inthe first portion is less than 9E18 per cm³.
 29. The device of claim 26wherein the tub dopant concentration in the second portion is between1E16 per cm³ and 1E19 per cm³ and the tub dopant concentration in thefirst portion is less than 9E18 per cm³.
 30. The device of claim 26wherein the tub dopant concentration in the second portion isapproximately 1E18 per cm³ and the tub dopant concentration in the firstportion is approximately 5E17 per cm³.